Question

Cache block size (B) can affect both miss rate and miss latency. Assuming a machine with a base CPI of 1, and an average of 1.35 references (both instruction and data) per instruction, find the block size that minimizes the total miss latency given the following miss rates for various block sizes. 8:4% 16:3% 32:2% 64: 1.5% 128:1% a. [10] What is the optimal block size for a miss latency of 20 x B cycles? b. [10] What is the optimal block size for a miss latency of 24 + B cycles? C. [10] For constant miss latency, what is the optimal block size?

Answer 1

The optimal block size for miss latency of 20xB cycles is 8 bytes block size, The optimal block size for miss latency of 24+B cycles is 32 bytes block size, The optimal block size for constant miss latency is 128 bytes block size.

The optimal block size is the block size with the lowest average memory access time. For calculate the average memory access time we can use miss latency and latency from the cycles and the block size. So,

average memory access time = 1 + miss latency * latency

For the first question, since is have 20xB cycles so the latency is,

latency = 20 * block size.

The detail calculation in attached images. So, we can see the lowest average memory access time for 8 bytes block size.

For the second question, since is have 24+B cycles so the latency is,

latency = 20 + block size.

The detail calculation in attached images. So, we can see the lowest average memory access time for 32 bytes block size.

For the third question, since the miss latency is constant we don't need to calculate anymore, we just see the lowest miss latency which is 128. So, the optimal block size is 128 bytes.

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