Consider the LEGV8 code below. Assume that X1 is initialized to 11 and X2 is initialized to 22. ADDI X1, X2, #5 ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X1, X1 (a) Suppose you executed the code on a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). Show the pipeline timing diagram below when the code is executed. ADDI X1, X2, #5 IF ID EX МЕМ WB ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X1, X1 (b) What would the final values of registers X3 and X4 be? (c) What would the final values of register X5 be? Assume the register file is written at the beginning of the cycle and read at the end of a cycle. Therefore, an ID stage will return the results of a WB state occurring during the same cycle. See Section 4.7 and Figure 4.51 for details. (d) Suppose you executed the code below on a pipeline from Section 4.5 that uses data forwarding for handling data hazards. Show the pipeline timing diagram below: ADDI X1, X2, #5 IF ID EX МЕМ WB ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X3, X2

Respuesta :

Except for instructions and the stack, LEGv8 does not require words to be aligned in memory.

What are the eventual values of register X5?

LEGv8 Registers n X0 - X7:

procedure arguments/results n X8:

n X9 - X15: indirect result location register

temporaries n X16 - X17 (IP0 - IP1):

may be used as a scratch register by the linker, other times as a temporary register n X18:

n X19 - Platform register for platform independent code; otherwise, a temporary register

n C code: f = (g + h) - I + j);

n f,..., j in X19, X20,..., X23 n

Compiled LEGv8 code:

f = (g + h) - I + j);

ADD X9, X20, X21

ADD X10, X22, X23

SUB X19, X9, X10

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