for a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. hw 5.5 table. bits 31-10 are the tag. bit 9-5 are the index. bits 4-0 are the offset. (a) what is the cache block size (in words)? (b) how many blocks does the cache have? (c) what is the ratio between total bits required for such a cache implementation over the data storage bits? beginning from power on, the following byte-addressed cache references are recorded. (d) byte-addressed cache references in hex and dec. address 1 is 00 (hex), 0 (dec). address 2 is 04 (hex), 4 (dec). address 3 is 10 (hex), 16 (dec). address 4 is 84 (hex), 132 (dec). address 5 is e8 (hex), 232 (dec). address 6 is a0 (hex), 160 (dec). address 7 is 400 (hex), 1024 (dec). address 8 is 1e (hex), 30 (dec). address 9 is 8c (hex), 140 (dec). address 10 is c1c (hex), 3100 (dec). address 11 is b4 (hex), 180 (dec). address 12 is 884 (hex), 2180 (dec). for each reference, list (1) its tag, index, and offset, (2) whether it is a hit or a miss, and (3) which bytes were replaced (if any). (e) what is the hit ratio? (f) list the final state of the cache, with each valid entry represented as a record of . for example, <0, 3, mem[0xc00]-mem[0xc1f]>

In this situation, the word size is 32 bits = 4 bytes and we will assume byte-addressable memory. As the offset field is of 5 bits(4-0) therefore, cache block size = 2^5 bytes = 2^5 / 2^2

= 2^3 words

= 8 words.

As the index field is of 5 bits(9-5) therefore, number of entries in the cache = 2^5 = 32 entries.

We will assume 1 valid bit is there for each tag along with the tag bits.

Therefore per block, we have:-

data bits = 8*32 = 256 bits.

tag bits = 22 bits

valid bits = 1 bit.

Therefore, the total bits needed to implement the cache per block = 256 + 22 + 1 = 279 bits

Therefore ratio of total bits over data storage bits = total bits / data bits

= 279 / 256

= 1.089

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