We have that the Processor speed reducing will be is mathematically given as
From the question we are told
Generally we have that the processor fetches directions at a charge of 1m guidelines per 2d or 1 MIPS.
The I/O machine switch records at a pace of 19200 bits per seconds.
[tex]\frac{19200}{8} = 2400[/tex]
Therefore
2400 bytes per sec
Since that CPU is fetching and executing guidelines at an common charge of one million directions per 2nd sluggish down or cycle wasted p.c in DMA switch = ( 2400 / 1000000) * 100
= 0.24%
Hence
The Processor speed reducing down will be
S=0.24 %.
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