Question

8.14 Consider a system in which bus cycles takes 500 ns. Transfer of bus control in either direction, from processor to I/O device or vice versa, takes 250 ns. One of the I/O devices has a data transfer rate of 50 KB/s and employs DMA. Data are transferred 1 byte at a time. a. Suppose we employ DMA in a burst mode. That is, the DMA interface gains bus mastership prior to the start of a block transfer and maintains control of the bus until the whole block is transferred. For how long would the device tie up the bus when transferring a block of 128 bytes? b. Repeat the calculation for cycle-​stealing mode.

Answer 1

Answer:

A) 2.56 ms

B) 128 μs

Explanation:

Time for Bus cycles = 500 ns

Transfer of bus control = 250 ns

I/0 device data transfer rate = 50 KB/s

Data are transferred at : 1 byte at a time

A) Determine how long the device tie up the bus when transferring a block of 128 bytes

Block size to be transferred = 128 bytes

Bandwidth = 50 KB/s

data transfer = (Block size ) / ( Bandwidth)

                     = ( 128 * 8 ) / ( 50 * 10^3 * 8 )

                     = ( 1024 ) / ( 50 * 10^3 * 8 )

                     = 2.56 ms

To determine the actual transfer time  we have to add up the transfer time for the bus control in both directions :

2.56 ms + 500 ns = 2.56 ms. this is because 500 ns is not a significant value

B) cycle stealing mode

In this mode each byte is transferred at a time and The total transfer time needed for the bus control in both directions will be double the total time i.e 2 * 500 ns = 1000 ns. because additional control time of  250 ns is required at both ends

since 1 byte is transferred at a time , 1 byte will be transferred in 1 μs

128 bytes = 128 *  1 μs = 128 μs

Answer 2

Following are the solution to the given points:

Given:

• $600\ ns$ is the time it takes for a bus to cycle.
• The bus control will be used to transmit data in both directions, as from the CPU to the I/O devices and from the I/O devices to a processor, and so this transfer takes $350 \ ns$.
• One of the I/O devices that employ Direct Memory Access (DMA) has a bandwidth of $60\ \frac{KB}{s}$.

For point a:

• The DMA is being used in burst mode, the DMA will take over access well before data transmission, then lose control just after data transmission until the DMA maintains its interfaces throughout the entire process.
• The size of the transferable block is 256 bytes.
• The following is an example of a typical data transmission operation:
• Block size for data transfer Bandwidth So "blocksize" is "256 bytes" as well as the "bandwidth" is "60 KBps" in this case.

             $\to \bold{Data \ transfer =\frac{(256 \times 8)} {(50 \times 10^3 \times 8)} = 5.12 \times 10^{-3} = 5.12\ ms}$

• As a result, the standard transfer operation will take 5.12 ms.
• Whenever the bus control transfer time is factored in, both the taking of bus control and the release of bus control require 350 ns.
• Including bus control $= 250 ns +2.56 ms +250 ns = 2.56 ms +500 ns$
• Including bus control $= 350ns + 5.12ms + 350ns = 5.12ms + 700ns$
• The 600 ns is a small quantity that can be ignored. As a result, the time it takes to transport 256 bytes is 5.12ms.
• As just a result, the time required to transfer 256 bytes of data is 5.12ms.

For point b:

Cycle Stealing Mode:

• It's Random Access Memory is accessible without interacting with the  CPU in cycle stealing mode, just as DMA.
• Every byte is sent a few at a time in this approach. It after every byte's data transfer, local bus control is acquired and then released.
• Its bus control took 600 ns in regular mode but 350 ns in this mode just at the start and finish of bus control.
• It is necessary to have a total of 1000 ns, as illustrated below:

            $\to 1000 \ ns= 1000 \times 10^{-9}=10^{-6}= 1 \ \mu$

• As a result, each byte takes $\bold{1\ \mu}$, and also the data block has 256 bits, so the data transfer process takes 256 micro-sec.

As a result, the time required to transport 256 bytes is 256 microseconds.

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