Question

We have a combinatorial logic function that can be decomposed into three steps each with the indicated delay with a resulting clock speed of 5.26 GHz.
1. 65ps
2. 45ps
3. 60ps
4. Reg 20ps
Assume we further pipeline this logic by adding just one additional register between the first two or last two stages of combinatorial logic. What would be the highest resulting clock speed we could achieve in GHz?
We have a combinatorial logic function that can be decomposed into three steps each with the indicated delay with a resulting clock speed of 4.76 GHz.
1. 65ps
2. 55ps
3. 70ps
4. Reg 20ps
Assume we further pipeline this logic by adding just one additional register between the first two or last two stages of combinatorial logic. What would be the highest resulting clock speed we could achieve in GHzi?

Answer 1

Answer:

1.    11.77 GHz

2.   11.11  GHz

Explanation:

1.

From the given information;

the highest resulting clock speed we could achieve in GHz is calculated as follows:

Using the formula:

highest resulting clock speed = 1/max (stage,stage,stage,stage) + register delay)

highest resulting clock speed = 1/max(65ps, 45ps, 60 ps) + 20ps)

highest resulting clock speed = 1/(65 + 20)ps

highest resulting clock speed =  1/85 ps

highest resulting clock speed = 0.01176470588  × 10¹² Hz

highest resulting clock speed = 1.17647059 × 10¹⁰ Hz

highest resulting clock speed =  1.177 × 10¹⁰ Hz

To Ghz; we have:

highest resulting clock speed = (1.177 × 10¹⁰/10⁹ )GHz

highest resulting clock speed = 11.77 Ghz

2.

Using the same formula from above;

highest resulting clock speed = 1/max(65ps, 55ps, 70 ps) + 20ps)

highest resulting clock speed = 1/(70 + 20)ps

highest resulting clock speed =  1/90 ps

highest resulting clock speed = 0.01111111111  × 10¹² Hz

highest resulting clock speed = 1.111111111  × 10¹⁰ Hz

highest resulting clock speed =  1.111 × 10¹⁰ Hz

To Ghz; we have:

highest resulting clock speed = (1.111 × 10¹⁰/10⁹ )GHz

highest resulting clock speed = 11.11 Ghz

Answer 2

In this exercise we have to calculate the delay time and the time to archive something, so we have that these times will be:

1) 11.77 GHz

2) 11.11  GHz

1) First we will use the knowledge to calculate the delay, so the formula can be used is:

$HRCS = 1/max (stage,stage,stage,stage) + register delay)\\HRCS = 1/max(65ps, 45ps, 60 ps) + 20ps)\\HRCS = 1/(65 + 20)ps\\HRCS= 1/85 ps\\HRCS = 0.01176470588* 10^{12}Hz\\HRCS = 1.17647059 * 10^{10} Hz\\HRCS = 1.177 * 10^{10} HZ\\HRCS = 11.77 Ghz$

2) through the first formula we can also calculate the time for the speed of archiving, like this:

$HRCS = 1/max(65ps, 55ps, 70 ps) + 20ps)\\HRCS = 1/(70 + 20)ps\\HRCS = 1/90 ps\\HRCS = 0.01111111111 * 10^{12} Hz\\HRCS = 1.111111111 * 10^{10} Hz\\HRCS = 11.11 Ghz$

See  more about GHZ at brainly.com/question/13112545