The architecture above is the MIPS architecture. Each instruction is executed in 5 clock cycles. Is it true that all MIPS programs are slower than MARIE programs. Why or why not? MIPS is a 5-stage computer architecture. Assume that there are 5 pipelines, what is the speedup over non-pipelined MIPS architecture, please explain with the help of a picture. Using the instruction ADD R1 R2 R3, what components is not used from the above. Please circle in the picture what are the values of instructions[31:0]? what are the values of the ALU control?
