Design a FSM to detect the sequence 101 into an input called x. The output z = 1 when the sequence has been detected and z = 0 otherwise. Detect the sequence continuously, also assume a Moore model is used to describe the output. Below you will find a set of input and output values you can use for testing purposes. x = 1001010100101 z = 0000010100001 You will need a debouncer for this circuit. I have performed this Google search, "verilog debouncer", and found several.
Create a Verilog program to describe the FSM given above. Use the state table to describe the FSM, then simulate, program the FPGA and test circuit for correctness.
