A VLSI designer plans to pipeline a data path using D-type flip-flops with
tclk-to-Q=47 psec, tsetup = 24 psec and thold = 44 psec. If a 1038 MHz
clock is used with a maximum clock skew of 63 psec, and there are a
minimum of 2 logic gates between flip-flops, each having a gate delay of 30
psec, then what is the timing margin for hold time analysis in picoseconds?
Answer:
