Draw the state diagram for a Moore FSM that has a 1-bit input P and a 1- bit output Q. P will be either 1 or 0 on any particular clock cycle. Q=0 if P has been 1 for an even number of clock cycles; Q=1 if P has been 1 for an odd number of clock cycles. a. Draw the state diagram for this Moore FSM. b. Draw the state table for this FSM. c. Draw a state assigned table for this FSM. The state should be the same as the output: Q. d. Draw the truth table for this FSM’s next-state variable. e. Derive the expression for the next state variable and the output Q. f. Draw the circuit for this FSM. If done properly, the circuit you create will implement a component that you have seen before. What component have you implemented
