Consider executing the following code on a 5-stage MIPS pipeline processor that supports data forwarding:
ADD $3, $2, $1
ADD $5, $3, $7
SUB $4, $3, $5
ADD $6, $7, $1
ADD $8, $4, $6
Show the 5-stage pipeline timing diagram. Which registers are being read and which register will be written at the end of the fifth cycle of execution?
