also the logic blocks used to implement this datapath have the following latencies: inst. mem. adder mux alu reg. file (r/w) data mem. control block imm. gen. 400ps 80ps 10ps 100ps 150ps 350ps 100ps 100ps and costs: inst. mem. adder mux alu reg. file data mem. control block imm. gen. 1000 50 5 100 200 2000 500 300 consider the addition of a multiplier to the alu. this addition will add 300ps to the latency of the alu and will add a cost of 600 to the alu. the result will be 5% fewer instructions executed since we will no longer need to emulate the mul instruction. (note: ignore latencies and costs for components not mentioned here, such as pc and single gates.) a) what is the (minimum) clock cycle time with and without this improvement? (5 points) b) what is the speedup achieved by adding this improvement? (3 points) c) get the cost/relative performance ratio (using the performance before the improvement as the referenced performance) with and without this improvement and compare. from that point of view, do you recommend the improvement? (7 points)
