ssume that we have a simple processor which is able to execute 7 instructions: load doubleword (ld), store double world (sd), add (add), subtract (sub), and (and), or (or), and branch if equal (beq). assume the operation times for the major functional units are in the table (assuming target address for beq instructions is calculated by alu): inst. fetch reg. read alu operation data mem. reg. write 200ps 150ps 200ps 300ps 150ps a) if the processor is in single-cycle model, what are total times for load doubleword (ld), store doubleword (sd), r-format (add, sub, and, or), and branch if equal (beq) instructions, respectively (not counting the idle time within a clock period)? what is the (minimum) clock period? (10 points) b) if the processor is 5-stage pipelined (with steps inst. fetch, reg. read, alu operation, data mem., and reg. write), what is the (minimum) clock period? what is the execution time for a load doubleword (ld) instruction? (5 points) c) suppose the following instructions run on the processor. ld x1,0(sp) ld x10,8(sp) add x7,x5,x6 what is the execution time if the processor is in single-cycle model? what is the execution time of the instructions in b) on the pipelined processor? what is the speedup comparing to the single-cycle processor? (5 points)
